Youngbin Kim, Jian Cai, Yooseong Kim, Kyoungwoo Lee, Aviral Shrivastava, “Splitting functions in code management on scratchpad memories”, International Conference On Computer Aided Design (ICCAD), Nov, 2016.Jian Cai, Yooseong Kim, Youngbin Kim, Aviral Shrivastava, Kyoungwoo Lee, “Reducing code management overhead in software-managed multicores”, Design, Automation & Test in Europe Conference & Exhibition (DATE), Mar, 2017.The evaluation shows that our optimization technique improves performance by 16% on average, which can only be achieved by using 20% more SPM space if without function-splitting. In this work, we proposed a function splitting technique that mitigate these fundamental limitations. Our approach is based on postpass analysis and optimization techniques, and it handles the whole program, including libraries. Our technique loads required code segments into the SPM on demand at runtime.
Therefore, their performance is limited by the existing calling relationships between functions and the code size of the functions. In this paper, we propose a fully automatic dynamic scratch-pad memory (SPM) management technique for instructions.
Although there have been many studies to find a good mapping from the given program and SPM size, they keep the call graph and functions of the program unchanged. In this scheme, SPM is divided multiple regions and functions of a program are mapped to the one of the regions. Overlay-based technique is a popular method to mange the code using a SPM. Data transfer between main memory and the SPM should be managed either by programmer or compiler, typically via the direct memory access (DMA) instructions. On the other hand, the benefit comes at the cost of explicit management of data. It has been studied as a scalable and energy-efficient alternative to the caches since it has simple design and does not increase the unnecessary traffic in the bus as the core scales. Scratchpad Memory (SPM) is a software-managed SRAM memory, which does not have hardware logics to automatically capture the locality (e.g. While cache has been adopted widely to accelerate the memory accesses transparently, it is getting more difficult to maintain cache-based architecture in the many-core systems, mainly due to the cache coherency traffic. 16, no 4, article id 112Ĭode management, Hard real-time systems, Scratchpad memory (SPM), Worst-case execution time (WCET), Codes (symbols), Embedded systems, Industrial management, Integer programming, Interactive computer systems, Mapping, Memory architecture, Optimization, Polynomial approximation, Automotive applications, Direct memory access, Dynamic management, Integer Linear Programming, Scratch pad memory, Worst-case execution time, Real time systems National CategoryĬomputer Systems Identifiers URN: urn:nbn:se:kth:diva-216507 DOI: 10.1145/3063383 ISI: 000425114000022 Scopus ID: 2-s2.0-85019904220 OAI: oai:DiVA.As the number of core increases, scalability is becoming an important criteria in computer architecture design. Place, publisher, year, edition, pagesAssociation for Computing Machinery, 2017. The results show that our techniques can significantly reduce the WCET estimates compared to caches with the state-of-the-art cache analysis. We evaluate our techniques using the Mälardalen WCET suite, MiBench suite, and proprietary automotive applications from industry. Based on ILP, it can also find an optimal mapping. The third technique maps functions directly to SPM addresses, not using regions, which can further reduce the WCET. The first technique finds an optimal mapping of each function to a region using integer linear programming (ILP), whereas the second technique is a polynomial-time heuristic that is suboptimal. These techniques perform allocation at the granularity of functions, with the objective of minimizing the impact of DMA overhead to the worst-case execution time (WCET) of a given program. In this article, we present three function-level code management techniques. Code management techniques try to minimize the overhead of DMA operations by finding an allocation scheme that leads to efficient utilization. In dynamic management of instruction SPMs, code blocks are dynamically copied from the main memory to the SPM at runtime by executing direct memory access (DMA) instructions. One way of such management is dynamic management. SPM has time-predictable characteristics since its data movement between the SPM and the main memory is entirely managed by software. Scratchpad memory (SPM) is a promising on-chip memory choice in real-time and cyber-physical systems where timing is of the utmost importance. 16, no 4, article id 112 Article in journal (Refereed) Published Abstract 2017 (English) In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol.
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